Methods and systems for distributing clock and reset signals across an address macro
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United States of America Patent
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Oct 11, 2016
Issued Date -
N/A
app pub date -
Jan 31, 2014
filing date -
Apr 19, 2013
priority date (Note) -
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Abstract
A distribution network for distributing clock and reset signals across an address macro has circuit blocks having dividers and counters, drivers connected in a balanced tree, and drivers connected in an unbalanced tree. The dividers and counters are synchronized relative to a clock signal. The drivers connected in the balanced tree distribute the clock signal synchronously to the circuit blocks. The drivers connected in the unbalanced tree distribute a reset signal to the circuit blocks. The clock signal is distributed via the balanced tree as a function of the reset signal.
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