Circuit for mitigating write disturbance of dual-port SRAM
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United States of America Patent
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Oct 11, 2016
Grant Date -
Jan 28, 2016
app pub date -
Jan 22, 2015
filing date -
Jul 24, 2014
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Abstract
A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates.
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