Memory architecture dividing memory cell array into independent memory banks

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United States of America Patent

PATENT NO 9466355
APP PUB NO 20150332751A1
SERIAL NO

14711782

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Abstract

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A memory architecture includes K first wordlines, M groups of second wordlines, a memory cell array and M switch circuits. K and M are positive integers. Each group of second wordlines includes a plurality of second wordlines. The memory cell array includes M memory banks. The M memory banks are coupled to the M groups of second wordlines respectively, and receive independent M sets of second wordline signals through the M groups of second wordlines respectively. M switch circuits are disposed in correspondence with the M memory banks respectively. Each switch circuit selectively couples the K first wordlines to a corresponding memory bank so that the corresponding memory bank receives a shared set of first wordline signals through the K first wordline. Each memory bank performs a data access operation according to the received set of first wordline signals and a corresponding set of second wordline signals.

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Patent Owner(s)

Patent OwnerAddress
PIECEMAKERS TECHNOLOGY INC9F-1 NO 89 DONGMEI RD EAST DIST HSINCHU CITY

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ting, Tah-Kang Joseph Taipei, TW 35 209
Wang, Gyh-Bin Hsinchu County, TW 24 196

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