System and method for offsetting the data buffer latency of a device implementing a JEDEC standard DDR-4 LRDIMM chipset
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United States of America Patent
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Sep 20, 2016
Grant Date -
Oct 15, 2015
app pub date -
Mar 20, 2015
filing date -
Mar 21, 2014
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Abstract
A system and method for offsetting the data buffer latency in a CPIO device having a JEDEC standard DDR-4 LRDIMM chipset as the front end is disclosed. According to one embodiment, a CPIO ASIC provides variable timing control for its DDR-4 LRDIMM interface such that propagation delay of the data buffers can be offset by the CPIO ASIC, allowing the CPIO LRDIMM to be timing compatible with an RDIMM.
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