Integrated circuit layout structure and method having different cell row heights with different row ratios for area optimization
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United States of America Patent
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Sep 20, 2016
Grant Date -
Jul 21, 2016
app pub date -
Jan 20, 2015
filing date -
Jan 20, 2015
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Abstract
An integrated circuit layout structure and method thereof establishes cell rows with different cell heights for accommodating cells with corresponding heights, such that an area of an integrated circuit can be fully utilized. Therefore, it reduces an area wasted by an unnecessary uniform cell height, so as to improve integration of the integrated circuit.
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