Timer unit circuit having plurality of output modes and method of using the same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 20, 2016
Grant Date -
Mar 26, 2015
app pub date -
Dec 4, 2014
filing date -
Nov 21, 2007
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A timer unit having a first output mode and a second output mode, the timer unit includes a first register that stores a first value, a second register that stores a second value, a third register that stores a third value, a counter that generates a count signal based on the first value, and an output circuit that outputs a first output signal and a second output signal. When the timer unit is set in the first output mode, the output circuit outputs the first output signal having a pulse width determined by the count signal and the second value, and outputs the second output signal having a pulse width determined by the count signal and the third value. When the timer unit is set in the second output mode, the output circuit outputs the first output signal having a pulse width determined by the count signal, the second value and the third value.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully