Low latency digital jitter termination for repeater circuits
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United States of America Patent
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Sep 13, 2016
Grant Date -
May 28, 2015
app pub date -
Jul 25, 2011
filing date -
Jul 25, 2011
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Abstract
A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.
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