Double phase-locked loop with frequency stabilization
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United States of America Patent
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Sep 13, 2016
Grant Date -
Aug 6, 2015
app pub date -
Jan 13, 2015
filing date -
Jan 31, 2014
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Abstract
A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source. The second clock has a frequency close to said first clock. The first loop has a bandwidth at least an order of magnitude less than the second loop. A coupler couples the first and second phase-locked loops to provide a common output. The double phase-locked loop can be used, for example, to provide time-of-day information in wireless networks or as a fine filter for cleaning phase noise from clock signals recovered over telecom/datacom networks.
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