VSL-based VT-compensation and analog program scheme for NAND array without CSL
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 13, 2016
Grant Date -
Feb 18, 2016
app pub date -
Aug 17, 2015
filing date -
Aug 17, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A YUKAI NAND array comprising multiple strings of all TLC and mixed TLC+SLC memory cells associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) with full BL-shielding without wasting extra silicon area and without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding to perform concurrent ABL, AnP and Alt-WL program under multi-passes program schemes with LBL program voltage compensations and half-BL Odd/Even program-verify and read operations with individual VSL-based Vt-compensation to mitigate high WL-WL and BL-BL coupling effects.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully