Thin film transistor array panel including layered line structure and method for manufacturing the same
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United States of America Patent
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Aug 30, 2016
Grant Date -
Dec 10, 2015
app pub date -
Aug 17, 2015
filing date -
Nov 17, 2004
priority date (Note) -
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Abstract
The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).
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