Sampling clock adjustment for an analog to digital converter of a receiver
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United States of America Patent
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Aug 23, 2016
Grant Date -
Jun 16, 2016
app pub date -
Dec 16, 2014
filing date -
Dec 16, 2014
priority date (Note) -
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Abstract
A receiver for high speed communications. The receiver includes an analog to digital converter to convert an analog input signal into at least one digital input signal at timings controlled by a sampling clock. A finite impulse response filter generates at least one filtered input signal based on the digital input signal. A data decision circuit recovers data based on the filtered input signal. The filtered input signal and the recovered data can be provided to a feedback loop to determine a timing error of the sampling clock, which is then used to generate the sampling clock.
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