Passive equalizer
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United States of America Patent
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Aug 16, 2016
Grant Date -
Jun 18, 2015
app pub date -
Dec 11, 2014
filing date -
Dec 12, 2013
priority date (Note) -
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Abstract
Series resistance Rs is connected in series between an input terminal 1 and an output terminal 3, and a resonant circuit 11 including an inductor L1 and a capacitor C1, and a resonant circuit 13 including an inductor L3 and a capacitor C3 are connected between the input terminal 1 and the output terminal 3, in parallel to the series resistance Rs. One end of a shunt resistance R1 is connected to a connection point P1 of the inductor L1 and the capacitor C1, and the other end is connected to a ground destination. One end of a shunt resistance R3 is connected to a connection point P3 of the inductor L3 and the capacitor C3, and the other end is connected to the ground destination.
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