Semiconductor device and method
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
Aug 2, 2016
Issued Date -
N/A
app pub date -
Jan 9, 2015
filing date -
Jan 9, 2015
priority date (Note) -
Withdrawn
status (Latency Note)
Importance
Abstract
Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.
First Claim
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International Classification(s)
- 2015 Application Filing Year
- H01L Class
- 25498 Applications Filed
- 22451 Patents Issued To-Date
- 88.06 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- H01L Class
- 0 % this patent is cited more than
- 9 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Feb 2, 2028 |