Binary frequency shift keying with data modulated in digital domain and carrier generated from intermediate frequency
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 26, 2016
Grant Date -
Oct 15, 2015
app pub date -
Apr 11, 2014
filing date -
Apr 11, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. Depending on the binary data ‘1’ or ‘0’ to be transmitted, ‘M’ or ‘M+1’ clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used to generate N pulse width modulated (PWM) phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize a sine waveform whose lower harmonics are substantially suppressed.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully