Multiple silicide integration structure and method
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United States of America Patent
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Jul 12, 2016
Grant Date -
Jul 23, 2015
app pub date -
Mar 30, 2015
filing date -
Feb 11, 2010
priority date (Note) -
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Abstract
A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices.
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