Sample and hold switch circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 28, 2016
Grant Date -
Jul 16, 2015
app pub date -
Sep 16, 2014
filing date -
Jan 16, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A sample and hold switch circuit includes a clock generation sub-circuit, a gate voltage bootstrap unit, a sampling Field Effect Transistor, a holding capacitor and a substrate selection sub-circuit which is connected with a signal input terminal, a signal output terminal and a substrate of the sampling Field Effect Transistor and arranged for selecting the signal input terminal or the signal output terminal to connect with the substrate of the sampling Field Effect Transistor according to the voltages of the analog signal inputted and the analog signal outputted. The sample and hold switch circuit reduces nonlinearity of the sampling Field Effect Transistor caused by its gate-source voltage changing with input signal, and eliminates bulk effect of the sampling Field Effect Transistor, thereby improving linearity of the sampling Field Effect Transistor, and extending dynamic range of the sample and hold switch circuit.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully