Reduced variation MOSFET using a drain-extension-last process

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United States of America Patent

PATENT NO 9379214
APP PUB NO 20150236117A1
SERIAL NO

14616964

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Abstract

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A MOSFET structure and method of manufacture that minimize threshold variations associated with statistical uncertainties of implanted source and drain extensions. The source and drain extensions are fabricated very late in the process using a material added to etched recesses immediately adjacent to the transistor's channel. In various embodiments, the added material may be germanium grown by selective epitaxy, doped silicon grown by selective epitaxy, or metallic materials created by deposition or by deposition and reaction.

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Patent Owner(s)

Patent OwnerAddress
SEMI SOLUTIONS LLC19160 BAINTER AVENUE LOS GATOS CA 95030

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kapoor, Ashok K Palo Alto, US 101 3596
Strain, Robert J San Jose, US 22 444

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