Dual PID controller based bit allocation and rate control for video coding
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United States of America Patent
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Jun 14, 2016
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N/A
app pub date -
Apr 20, 2011
filing date -
Apr 21, 2010
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Abstract
System and methods are provided for encoding a video stream. A video encoder may encode a frame and generate output bits to a buffer. A first PID controller may receive a first error signal and generate a preliminary bit budget for the frame, the first error signal being based on a complexity measure of the frame. A second PID controller may receive the preliminary bit budget, a second error signal and a predetermined bit rate setting, the second error signal being representative of a difference between a target number of bits stored in the buffer and a feedback status of the buffer. The second PID controller may generate a final bit budget for the frame, and provide the final bit budget for the frame to the video encoder.
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