Circuit arrangement, device and method for 5B/6B coding
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United States of America Patent
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Jun 14, 2016
Grant Date -
Jul 23, 2015
app pub date -
Nov 24, 2014
filing date -
May 25, 2012
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Abstract
A circuit arrangement for determining and providing a first information I1−, that in a digital input word A B C D E comprising a first input bit A, a second input bit B, a third input bit C, a fourth input bit D and a fifth input bit E, at most only one of the five input bits A, B, C, D, E comprises the value 1 (“high”), a second information I2, that in the input word A B C D E exactly two of the five input bits A, B, C, D, E comprise the value 1 (“high”), a third information I3, that in the input word A B C D E exactly three of the five input bits A, B, C, D, E comprise the value 1 (“high”) and a fourth information I4+, that in the input word A B C D E at least four of the five input bits A, B, C, D, E comprise the value 1 (“high”).
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