Method and apparatus for designing and generating a stream processor
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United States of America Patent
Stats
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Jun 14, 2016
Grant Date -
Dec 27, 2012
app pub date -
Jun 22, 2011
filing date -
Jun 22, 2011
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Embodiments of the invention provide a method and apparatus for generating programmable logic for a hardware accelerator, the method comprising: generating a graph of nodes representing the programmable logic to be implemented in hardware; identifying nodes within the graph that affect external flow control of the programmable logic; retaining the identified nodes and removing or replacing all nodes which do not affect external flow control of the programmable logic in a modified graph; and simulating the modified graph or building a corresponding circuit of the retained nodes.
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International Classification(s)
Cited Art Landscape
Patent Citation Ranking
- 17 Citation Count
- G06F Class
- 65.80 % this patent is cited more than
- 9 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Dec 14, 2027 |
