Instruction based interrupt masking for managing interrupts in a computer environment

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United States of America Patent

PATENT NO 9361114
SERIAL NO

11296651

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Abstract

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Managing interrupts in a computing environment includes executing an instruction, deriving an interrupt mask value based at least in part on the instruction being executed, performing a masking operation involving the interrupt mask value and at least one pending interrupt to determine whether a pending interrupt is allowable, and in the event that the pending interrupt is allowable, performing the interrupt.

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Patent Owner(s)

Patent OwnerAddress
AZUL SYSTEMS INC1600 PLYMOUTH STREET MOUNTAIN VIEW CA 94043

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Choquette, Jack Mountain View, US 47 253
Sellers, Scott Menlo Park, US 24 578
Tene, Gil Los Altos Hills, US 53 789
Wolf, Michael A San Francisco, US 53 1372

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