LDPC decoder variable node units having fewer adder stages
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United States of America Patent
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May 31, 2016
Grant Date -
May 27, 2010
app pub date -
Nov 26, 2008
filing date -
Nov 26, 2008
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Abstract
In one embodiment, the present invention is a variable node unit (VNU) of a low-density parity-check (LDPC) decoder. The VNU receives a soft-input value and wc check node messages, where wc is the column hamming weight of the LDPC code. The VNU generates (i) an extrinsic log-likelihood ratio (LLR) by adding all wc check node messages together; (ii) a hard-decision output by adding the extrinsic LLR to the soft-input value and selecting the sign bit of the resulting sum; and (iii) wc variable node messages. Each variable node message is generated by adding a different set of (wc−1) check node messages to the soft-input value where each set excludes a different check node message. In so doing, VNUs of the present invention may generate variable node messages using fewer adder stages compared to prior-art VNUs such that throughput may be increased over that of prior-art VNUs.
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