Method and apparatus for camouflaging a standard cell based integrated circuit
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United States of America Patent
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May 31, 2016
Grant Date -
Jul 25, 2013
app pub date -
Mar 7, 2013
filing date -
Feb 24, 2009
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Abstract
A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logic cells to make it difficult for reverse engineering programs to be used to discover the circuit's function.
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