Reduced dynamic power D flip-flop
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United States of America Patent
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May 24, 2016
Grant Date -
Aug 20, 2015
app pub date -
May 30, 2012
filing date -
May 30, 2012
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Abstract
A CMOS D-type flip flop (D-FF) exhibits reduced power consumption by selectively disabling certain charging/discharging operations at specific circuit elements to minimize the capacitance of the circuit's internal nodes using a partial signaling technique. A clock inverter module may be used to provide a partial inverse clock signal that is the complement of a clock signal when a non-clock dependent input to the clock inverter module has a first value and to provide a fixed signal when the non-clock dependent signal has a second value. One or more MOSFETs controlled by the partial inverse clock signal do not charge or discharge when the non-clock dependent signal has the second value.
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