Method of manufacturing stacked package
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United States of America Patent
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May 24, 2016
Grant Date -
Aug 13, 2015
app pub date -
Apr 17, 2014
filing date -
Feb 11, 2014
priority date (Note) -
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Abstract
A method of manufacturing a stacked package includes a first process of stacking a semiconductor chip on an upper surface of a PCB having a wiring pattern and a via-hole pad, a second process of forming a photoresist (PR) layer on the upper surface of the PCB having the semiconductor chip and the via-hole pad, a third process of removing the photoresist layer of a remaining region except for an upper portion of the via-hole pad so that a photoresist layer of a via-hole region remains only at the upper portion of the via-hole pad, a fourth process of forming a molding layer by molding the upper surface of the PCB having the semiconductor chip to expose an upper surface of the photoresist layer of the via-hole region, and a fifth process of removing the photoresist layer of the via-hole region to form a via-hole on the via-hole pad.
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