Memory interface
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United States of America Patent
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May 24, 2016
Grant Date -
Aug 6, 2015
app pub date -
Feb 3, 2014
filing date -
Feb 3, 2014
priority date (Note) -
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Abstract
A data path interface for transferring data to a memory device, comprising: programmable delay units (“PDUs”), wherein data is received by the interface according to a first clock signal and wherein the PDUs apply delays to the received data; and align blocks, wherein the align blocks select certain ones of the delayed data as a function of the first clock signal and a second clock signal, and wherein the selected certain ones of the delayed data are processed for transmission to the memory device according to the second clock signal.
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