Method and device for controlling the latency of electronic circuits
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United States of America Patent
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May 24, 2016
Grant Date -
May 29, 2014
app pub date -
Aug 30, 2011
filing date -
Sep 2, 2010
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Abstract
A device for monitoring the latency of electronic circuits based on microtechnology and/or nanotechnology, said circuits to be tested being supplied with the aid of a voltage Vdd, having a low level and a high level, for the detection of delay faults of said circuits, comprises: at least one device of type I placed between the high level of the power supply voltage and the elements of the circuit to be tested, and/or at least one device of type II placed between the low level of the power supply voltage of the elements of the elements of said circuit to be tested, the device of type I and the device of type II comprising at least one low-latency electrical path, said low-latency path being connected in parallel with a high-latency electrical path, a test signal monitoring the opening of the low-latency paths while the high-latency electrical paths are open.
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