Impedance matching network with high frequency switching
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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May 10, 2016
Grant Date -
Oct 8, 2015
app pub date -
Jun 5, 2015
filing date -
Nov 4, 2010
priority date (Note) -
In Force
status (Latency Note)
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Abstract
An impedance matching network having a plurality of reactance elements is disclosed. Each of the plurality of switching circuits comprises a first node and a second node; a first diode having an anode coupled to the first node and a cathode coupled to the second node; a second diode having an anode to couple to the second voltage line and a cathode to couple to the first node; and a transistor having a first, second, and control terminals. Each of the plurality of reactance elements is switched into the impedance matching network when the transistor in the respective one of the plurality of switching circuits is on and switched out after the transistor in the respective one of the plurality of switching circuits is off.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
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AES GLOBAL HOLDINGS PTE LTD | SINGAPORE 539775 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
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Mason, Christopher C | San Jose, US | 6 | 244 |
# of filed Patents : 6 Total Citations : 244 |
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Patent Citation Ranking
- 25 Citation Count
- H01J Class
- 93.87 % this patent is cited more than
- 9 Age
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11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Nov 10, 2027 |
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