Manufacturing method of wafer level chip scale package structure
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United States of America Patent
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May 10, 2016
Grant Date -
Apr 21, 2016
app pub date -
Apr 23, 2015
filing date -
Oct 20, 2014
priority date (Note) -
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Abstract
A manufacturing method of wafer level chip scale package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided. An active surface of one of the semiconductor devices has an active an active region and an outer region. A first electrode and a second electrode are arranged on the active region, and the outer region has a cutting portion and a channel portion. Next, a patterned protecting layer having a plurality of openings is formed on the active surface to respectively expose the first and second electrodes and channel portion. Subsequently, a wafer back thinning process is performed and then a back electrode layer is deposited. Subsequently, the channel portion is etched to form a trench exposing the back electrode layer, and a conductive structure connected to the back electrode layer is formed through the trench. Thereafter, the wafer is cut along the cutting portion.
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