Clock and data recovery circuit and method for estimating jitter tolerance thereof
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United States of America Patent
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May 3, 2016
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N/A
app pub date -
Jul 8, 2015
filing date -
Jul 8, 2015
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Abstract
A clock and data recovery circuit and a method for estimating jitter tolerance thereof are provided. A first phase signal is generated by a phase detector, and a second phase signal is used to generate a clock signal. The second phase signal is set to be identical to the first phase signal during an operation mode. A counting is started and the first phase signal is inversed to generate the second phase signal during a test mode. Whether a data signal has an error is determined. The counting is stopped to generate a count value when determining that the data signal has the error during the test mode. A tracing speed is computed according to the count value and a predetermined unit interval.
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