Group word line erase and erase-verify methods for 3D non-volatile memory
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United States of America Patent
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May 3, 2016
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Oct 27, 2014
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Feb 14, 2013
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Abstract
An erase operation for a 3D stacked memory device assigns storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.
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