Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
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United States of America Patent
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Apr 19, 2016
Grant Date -
Jun 23, 2011
app pub date -
Aug 13, 2009
filing date -
Sep 11, 2007
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Abstract
A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.
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