Methods and circuit structures for mitigating voltage stresses on printed circuit board (PCB) in high voltage devices

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United States of America Patent

PATENT NO 9313878
APP PUB NO 20140262445A1
SERIAL NO

14206366

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Abstract

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A method for mitigating voltage stress on a PCB includes applying AC voltage to a multi-terminal condenser structure of a multi-layered PCB. The terminal condenser structure is formed by overlapping a plurality of conductive traces between board layers of the multi-layered PCB. A corresponding dielectric layer is disposed between the overlapping conductive traces of the board layers. The overlapping conductive traces include a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal and the third terminal are disposed on a first layer of the multi-layered PCB, and the second terminal and the fourth terminal are disposed on a bottom layer of the multi-layered PCB. The first terminal and the second terminal are connected to a ground point, and the third terminal and the fourth terminal are connected to the AC voltage. Voltage stresses on the PCB are mitigated utilizing the multi-terminal condenser structure.

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Patent Owner(s)

Patent OwnerAddress
DOBLE ENGINEERING COMPANY85 WALNUT STREET WATERTOWN MA 02172

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Woodward,, Jr Robert Clark Cambridge, US 4 6

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