Event controlled decoding circuit
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United States of America Patent
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Apr 12, 2016
Grant Date -
Mar 3, 2016
app pub date -
Aug 27, 2014
filing date -
Aug 27, 2014
priority date (Note) -
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Abstract
A waveform generator circuit includes a memory with address locations storing output waveform defining data bits. An address counter generates an address for sequentially addressing the address locations in the memory. The memory responds by sequentially outputting the output waveform defining data bits at the addressed locations. An output circuit receives the waveform defining data bits output from the memory and operates to generate an output signal waveform having logic state values dependent on the sequentially output waveform defining data bits.
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