Zero cost NVM cell using high voltage devices in analog process
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United States of America Patent
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Apr 5, 2016
Grant Date -
Nov 15, 2012
app pub date -
May 10, 2012
filing date -
May 10, 2011
priority date (Note) -
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Abstract
A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate and a drift region to impart a programming voltage. Programming is effectuated using a drain extension which can act to inject hot electrons. The cell can be operated as a one-time programmable (OTP) or multiple-time programmable (MTP) device. The fabrication of the cell relies on processing steps associated with high voltage devices, thus avoiding the need for additional masks, manufacturing steps, etc.
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