Asymmetric log-likelihood ratio for flash channel

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United States of America Patent

PATENT NO 9305640
SERIAL NO

14724770

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Disclosed is a system and method for reading flash memory cells with dynamically adjusted probability values (e.g., log-likelihood ratios). In connection with reading bit values from flash memory cells, one or more predetermined first probability values are adjusted relative to one or more predetermined second probability values. The one or more predetermined first probability values are associated with reading one or more memory cells programmed to a first binary value, and the one or more predetermined second probability values are associated with reading one or more memory cells programmed to a second binary value. The plurality of bit values read from the plurality of non-volatile memory cells and the one or more adjusted first probability values are provided to a decoder for use in decoding the plurality of bit values.

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Patent Owner(s)

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WESTERN DIGITAL TECHNOLOGIES INC20511 LAKE FOREST DRIVE LAKE FOREST CA 92630

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hu, Xinde San Jose, US 58 950

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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges2621581362137774127158742501 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +010020030040050060070080090010001100120013001400150016001700

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