Parking address scheme for reducing risk of short circuits during memory readout
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United States of America Patent
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Apr 5, 2016
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app pub date -
Jan 13, 2015
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Jan 13, 2015
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Abstract
The invention comprises an improved process of reading out SRAM or like memory elements which utilize pre-charging of cell output buses. In the output configuration of the invention, Gray Code counter outputs are used as inputs in a decoder block, the decoder block being configured to output a valid column selection address for every two address inputs. These column outputs are mapped sequentially to the columns of the memory array, such that the columns are sequentially read out, each readout operation being interspersed with a parking interval. The Gray code address inputs reduce readout addressing errors and the parking interval creates a delay between cell readout operations that reduces glitch errors.
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