Package structure and packaging method of wafer level chip scale package
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 29, 2016
Grant Date -
Sep 17, 2015
app pub date -
Dec 18, 2014
filing date -
Mar 14, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A package structure and a packaging method of wafer level chip scale package are provided. The packaging method includes: providing a carrier, and disposing a plurality of chips on the carrier; forming a plurality of adhesive layers on a surface of the corresponding chips; covering a conductive cover plate, bonding the conductive cover plate with the chips through the adhesive layers, and dividing out a plurality of packaging spaces by the conductive cover plate for disposing the chips respectively; and providing an insulation material to fill the packaging spaces through via holes on the conductive cover plate to form a first insulation structure; finally, removing the carrier.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully