Forming vias and trenches for self-aligned contacts in a semiconductor structure
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United States of America Patent
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Mar 15, 2016
Grant Date -
Jul 10, 2014
app pub date -
Jan 10, 2013
filing date -
Jan 10, 2013
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Abstract
A semiconductor structure is formed to include a non-conductive layer with at least one metal line, a first dielectric layer, a first stop layer, a second dielectric layer, a second stop layer, a third stop layer and a fourth stop layer. A first photoresist layer is formed over the upper stop layer to develop at least one via pattern. The structure is selectively etched to form the via pattern in the third stop layer through the fourth stop layer. The first photoresist layer is then removed. A second photoresist layer is formed over the upper stop layer to develop a plurality of trench patterns, each of the trench pattern comprising a via-trench portion in which the trench pattern is formed above the via pattern, and a trench portion that is remaining part of the trench pattern.
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