Asynchronous programmable JTAG-based interface to debug any system-on-chip states, power modes, resets, clocks, and complex digital logic
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United States of America Patent
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Mar 1, 2016
Grant Date -
Jun 26, 2014
app pub date -
Mar 25, 2012
filing date -
Mar 25, 2012
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Abstract
An asynchronous debug interface is disclosed that allows TAG agents, JTAG-based debuggers, firmware, and software to debug, access, and override any functional registers, interrupt registers, power/clock gating enables, etc., of core logic being tested. The asynchronous debug interface works at a wide range of clock frequencies and allows read and write transactions to take place on a side channel, as well as within the on chip processor fabric without switching into a debug or test mode. The asynchronous debug interface works with two-wire and four-wire JTAG controller configurations, and is compliant with IEEE standards, such as 1149.1, 1149.7, etc., and provides an efficient and seamless way to debug complex system-on-chip states and system-on-chip products.
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