Apparatus and method for preventing multiple resets
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United States of America Patent
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Feb 2, 2016
Grant Date -
Nov 5, 2015
app pub date -
May 4, 2014
filing date -
May 4, 2014
priority date (Note) -
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Abstract
Multiple resets in a system-on-chip (SOC) during boot where on-board regulators and low voltage detector circuits have different trimmed and untrimmed values may be avoided by the inclusion of a series of latches that latch the trimmed values during boot and retain the trim values even during a SOC reset event. The SOC is prevented from entering into a reset loop during boot or when exiting reset for any reason other than boot. A power-on-reset comparator circuit that does not depend on any trim values enables the latches and only clears the latched trim values if its own supply voltage falls below a preset level.
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