Multi-processor bus and cache interconnection system
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United States of America Patent
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Feb 2, 2016
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N/A
app pub date -
Jun 27, 2014
filing date -
Mar 5, 2001
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Abstract
A multi-processor cache and bus interconnection system. A multi-processor is provided a segmented cache and an interconnection system for connecting the processors to the cache segments. An interface unit communicates to external devices using module IDs and timestamps. A buffer protocol includes a retransmission buffer and method.
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