SRAM write driver with improved drive strength
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United States of America Patent
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-
Jan 19, 2016
Issued Date -
Jul 16, 2015
app pub date -
Jan 14, 2014
filing date -
Jan 14, 2014
priority date (Note) -
Withdrawn
status (Latency Note)
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Abstract
A subsystem configured to write data to a static random access memory cell employs a single N-channel MOS device connected to ground in each leg of the bi-stable memory cell to overdrive the stored data. The subsystem implements the dual control required to effect matrix operation of the SRAM cell in the gate circuit of the single N-channel MOS device in the drive path. Specifically, the column select signal controls a semiconductor junction that interrupts the data connection to the gate. In this manner, the column select control is removed from the drive path, thus increasing drive strength. Further, a second semiconductor junction connects the gate of the single NMOS device in the drive path when the gate signal is interrupted.
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