Three-dimension (3D) integrated circuit (IC) package
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United States of America Patent
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Dec 29, 2015
Grant Date -
Jun 18, 2015
app pub date -
Dec 12, 2013
filing date -
Dec 12, 2013
priority date (Note) -
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Abstract
A three-dimension (3D) integrated circuit (IC) package is disclosed. The 3D IC package has a package substrate having a surface. At least one integrated circuit (IC) chip with or without suppressing a transient voltage and at least one transient voltage suppressor (TVS) chip are arranged on the surface of the substrate and electrically connected with each other. The IC chip is independent from the TVS chip. The IC chip and the TVS chip stacked on each other are arranged on the package substrate. Alternatively, the IC chip and the TVS chip are together arranged on an interposer formed on the package substrate.
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