Static offset reduction in a current conveyor
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United States of America Patent
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Apr 12, 2016
Grant Date -
Aug 14, 2014
app pub date -
Feb 7, 2014
filing date -
Feb 7, 2014
priority date (Note) -
Withdrawn
status (Latency Note)
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Abstract
The present document relates to voltage mirror circuits. A voltage mirror circuit, having an input node and an output node is configured to provide substantially equal voltage levels at the input node and the output node. The voltage mirror circuit comprises an input current source transistor, an input gain transistor arranged in series with the input current source transistor such that the input gain transistor is traversed by the bias current, wherein the voltage level at the input node corresponds to the voltage drop across the input current source transistor and the input gain transistor. An intermediate gain transistor forms a first current mirror with the input gain transistor. An output current source transistor forms a second current mirror with the intermediate current source transistor. An output gain transistor is wherein the voltage level at the output node corresponds to the voltage drop across the output current source transistor and the output gain transistor.
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