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• 15 United States
• 10 France
• 8 Japan
• 7 China
• 5 Korea
• 2 Other

Patent Owner(s)

Patent Owner	Address
SUBBANNAVAR CHAITHANYA B	Not Provided

International Classification(s)

• B02B:PREPARING GRAIN FOR MILLING; REFINING GRANULAR FRU....
• B02C:CRUSHING, PULVERISING, OR DISINTEGRATING IN GENERA....

• 2010 Application Filing Year
• B02B Class
• 16 Applications Filed
• 12 Patents Issued To-Date
• 75 % Issued To-Date

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Kumar, Naveen H C	Bangalore, IN	3	0
# of filed Patents : 3 Total Citations : 0
Subbannavar, Chaithanya B	Bangalore, IN	3	0
# of filed Patents : 3 Total Citations : 0

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• 0 Citation Count
• B02B Class

• 0 % this patent is cited more than
• 10 Age

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Maintenance Fees

Fee	Large entity fee	small entity fee	micro entity fee	due date
11.5 Year Payment	$7400.00	$3700.00	$1850.00	Jun 8, 2027

Fee	Large entity fee	small entity fee	micro entity fee
Surcharge - 11.5 year - Late payment within 6 months	$160.00	$80.00	$40.00
Surcharge after expiration - Late payment is unavoidable	$700.00	$350.00	$175.00
Surcharge after expiration - Late payment is unintentional	$1,640.00	$820.00	$410.00

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
December 08, 2015	US,9205429,B2   US9205429B2	GRANTED PATENT AS SECOND PUBLICATION
August 08, 2013	US,20130200191,A1   US20130200191A1	FIRST PUBLISHED PATENT APPLICATION

Full Text

US Patent No: 6831292

Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

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Abstract

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Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or 'FETs') that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

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Description

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Claims

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Legal Events

 

• FPAY2016
• FPAY2012
• AS2009
• REMI2008
• FPAY2008
• CC2005
• I2004
• STCF2004
• P2003
• AS2002
• F2002
• PD2001

Date	Code	Event	Description
Jun 14, 2016	FPAY	FEE PAYMENT	year of fee payment: 12
Jun 14, 2012	FPAY	FEE PAYMENT	year of fee payment: 8
Nov 22, 2009	AS	ASSIGNMENT	free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AMBERWAVE SYSTEMS CORPORATION;REEL/FRAME:023848/0183 Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Effective Date: Nov 22, 2009
Jun 23, 2008	REMI	MAINTENANCE FEE REMINDER MAILED
Jun 16, 2008	FPAY	FEE PAYMENT	year of fee payment: 4
Apr 05, 2005	CC	CERTIFICATE OF CORRECTION
Dec 14, 2004	I	Issuance
Nov 25, 2004	STCF	INFORMATION ON STATUS: PATENT GRANT	free format text: PATENTED CASE
Mar 27, 2003	P	Published
Nov 13, 2002	AS	ASSIGNMENT	free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CURRIE, MATTHEW;LOCHTEFELD, ANTHONY;HAMMOND, RICHARD;AND OTHERS;REEL/FRAME:013491/0885;SIGNING DATES FROM 20021023 TO 20021025 Owner name: AMBERWAVE SYSTEMS CORPORATION, NEW HAMPSHIRE
Sep 20, 2002	F	Filing
Sep 21, 2001	PD	Priority Date