Low-power internal clock gated cell and method
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United States of America Patent
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Dec 1, 2015
Grant Date -
Jun 11, 2015
app pub date -
May 15, 2014
filing date -
Dec 10, 2013
priority date (Note) -
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Abstract
A circuit includes a clock trigger block and a logic circuit. The logic circuit is configured to output a signal to the clock trigger block based on a logic level of an enable signal received at the logic circuit. The clock trigger block is configured to output an output signal response to a clock signal received at the clock trigger block and the signal received from the logic circuit.
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