Current-limited level shift circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 17, 2015
Grant Date -
N/A
app pub date -
Sep 5, 2014
filing date -
Jun 18, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A current-limited level shift circuit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first current-limiting unit, a second current-limiting unit, a first NMOS transistor and a second NMOS transistor, for providing a pair of input terminals and three pairs of output terminals outputting level shift signals. The first current-limiting unit is connected between the third output terminal and the fifth output terminal, and the second current-limiting unit is connected between the fourth output terminal and the sixth output terminal, for providing the current limiting of state transition. The pair of the first output terminal and the second output terminal, the pair of the third output terminal and the fourth output terminal, and the pair of the fifth output terminal and the sixth output terminal are selectively for providing multiple choices to the second stage.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully