Method for manufacturing a suspended membrane and dual-gate MOS transistor
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United States of America Patent
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Nov 10, 2015
Grant Date -
Mar 13, 2014
app pub date -
Nov 12, 2013
filing date -
Nov 23, 2009
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Abstract
A method for manufacturing a suspended membrane in a single-crystal semiconductor substrate, including the steps of: forming in the substrate an insulating ring delimiting an active area, removing material from the active area, successively forming in the active area a first and a second layers, the second layer being a single-crystal semiconductor layer, etching a portion of the internal periphery of said ring down to a depth greater than the thickness of the second layer, removing the first layer so that the second layer formed a suspended membrane anchored in the insulating ring.
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