Power disconnect unit for use in data transport topology of network on chip design having asynchronous clock domain adapter sender and receiver each at a separate power domain
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 3, 2015
Grant Date -
Jan 10, 2013
app pub date -
Jul 6, 2012
filing date -
Jul 6, 2011
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A power disconnect unit within a data transport topology of a NoC includes an asynchronous clock domain adapter unit inserted between a master side manager unit and a slave side manager unit. This configuration allows for the master and slave side managers of the power disconnect unit to be placed physically far apart on the chip, relieving the need to route long power rail signals on the chip. A response data path and associated asynchronous clock domain adapter unit is optionally included on the chip. A path to bypass the asynchronous clock domain adapter units is optionally included on the chip to enable a fully synchronous mode of operation without the data latency cost of the asynchronous adapter unit.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully